Implementation of ATLAS I:
a Single-Chip ATM Switch with Backpressure
Georgios Kornaros,
Dionisios Pnevmatikatos,
Panagiota Vatsolaki,
Georgios Kalokerinos,
Chara Xanthaki,
Dimitrios Mavroidis,
Dimitrios Serpanos, and
Manolis Katevenis
Institute of Computer Science (ICS)
Foundation for Research and Technology -- Hellas (FORTH)
Science and Technology Park of Crete,
P.O.Box 1385, Heraklion, Crete, GR 711 10 Greece
most authors are or were also with the
Department of Computer Science,
University of Crete, Greece.
Proceedings of the
IEEE Hot Interconnects VI Symposium,
Stanford University, California USA, 13-15 August 1998
© Copyright 1998 IEEE
ABSTRACT:
ATLAS I is a single-chip ATM switch with
10 Gb/s throughput, a shared buffer, 3 priority levels,
multicasting, load monitoring, and optional credit-based flow control.
This 6-million-transistor 0.35-micron CMOS chip
is about to be taped out for fabrication.
We present here the implementation of ATLAS I;
we report on the design complexity and silicon cost
of the chip and of the individual functions that it supports.
Based on these metrics,
we evaluate the architecture of the switch.
The evaluation points in the direction of
increasing the cell buffer size and
dropping VP/VC translation,
while other possible modifications are also discussed.
The cost of credit support (10% in chip area and 4% in chip power)
is minuscule compared to its benefits,
i.e. compared to what alternative architectures have to pay
in order to achieve comparable performance levels.