Other Research & Development Projects

The other current and past R&D projects of the Computer Architecture and VLSI Systems Group of ICS-FORTH are the following:

• G. Dimitriadis: An Arithmetic Entropy Codec VLSI Chip for JPEG Image Compression, Technical Report FORTH-ICS/TR-114, January 1994, 132 pages (in gzip'ed Postscript from ftp.ics.forth.gr).
• JBIG Fax Chip
• S-bus to TAXI Interface Chip Design
• P. Vatsolaki: Design of a High-Speed UART VLSI Library Cell, Technical Report FORTH-ICS/TR-50, June 1992, 72 pages (in compress'ed Postscript from ftp.ics.forth.gr).
• C. Xanthaki: A Memory Controller for Access Interleaving over a single Rambus, Technical Report FORTH-ICS/TR-124, July 1994, 56 pages (in compress'ed Postscript from ftp.ics.forth.gr).
• M. Katevenis: Fast Switching and Fair Control of Congested Flow in Broad-Band Networks, IEEE Journal on Selected Areas in Communications, Vol. SAC-5, No. 8, October 1987, pp. 1315-1326.
• M. Katevenis, S. Sidiropoulos, C. Courcoubetis: Weighted Round-Robin Cell Multiplexing in a General-Purpose ATM Switch Chip, IEEE Journal on Selected Areas in Communications, Vol. 9, No. 8, October 1991, pp. 1265-1279.
• S. Sidiropoulos: Fast Packet Switches for Asynchronous Transfer Mode, Technical Report FORTH-ICS/TR-25, August 1991, 69 pages (in compress'ed Postscript from ftp.ics.forth.gr).
• Parallel Supercomputer Architecture
• M. Katevenis, N. Tzartzanis: Reducing the Branch Penalty by Rearranging Instructions in a Double-Width Memory, ASPLOS-IV Proceedings (4th Int. Conf. on Architectural Support for Progr. Languages and Oper. Systems), Santa Clara, CA, ACM SIGARCH 19.2 - SIGOPS 25 - SIGPLAN 26.4, April 1991, pp. 15-27.
• Control Unit of a VHF Amplifier
• Microcontroller for the Intelligent Management of UPS Loads
• Data Logging System
• DC and Bipolar Step Motor Driver

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