The currently installed toolds are the following:
Analog, electical-level circuit simulator. Contemporary of Berkeley SPICE. Suitable for the simulation of any analog or digital circuit. Installation includes:
| Name | Functionality | Command |
| Star-HSPICE | Electrical-level Simulator | hspice |
| AvanWaves | Simulation Results Viewer | awaves |
For more information on using Star-HSPICE read the manual:
/vlsi/usr/carv1/avanti/98.2/docs/hspice.ps
Circuit design toolkit for logical and physical design. Tools include the following:
| Name | Functionality | Command |
| Opus Design Framework | Schematic and Layout Design | icfb |
| Leapfrog | Verilog/VHDL Simulator | cv, ev, sv |
| Pearl | Timing Analyser | pearl |
| Verilog Compiler | Compiler for Verilog | verilog |
For more information on using the Cadence tools read the manual by running openbook
Toolset for automatic placement and rooting of Deep Sub-Micron (DSM) designs. Silicon Ensemble is the graphical front-end tool which by invoking many point tools forms a Verilog/VHDL to Chip Layout methodology.
Tools include the following:
| Name | Functionality | Command |
| Silicon Ensemble | Front-end DSM tool | se |
| PBOPT | Standard Cell Placement Tool | pbopttool |
| CT-GEN | Clock Tree Generator Tool | ctgentool |
| Pearl | Timing Analyser | pearl |
| Warp Route | Rooter | wroute |
For more information on using the Cadence tools read the manual by running openbook
Toolset for Printed Circuit Board (PCB) design. Invoke the Project Manager front-end tool using the command projmgr.
For more information on using the Cadence tools read the manual by running openbook
Circuit synthesis toolset. Tools include the following:
| Name | Functionality | Command |
| Design Compiler | Synthesis Tool | design_analyzer |
For more information on using the Synopsys tools read the manual by running sold.