Technical Report FORTH-ICS/TR-124
Master of Science Thesis, Department of Computer Science, University of Crete
We have designed a memory controller for access interleaving over Rambus. Our controller maximizes the utilization of the bus, by interleaving the requests whenever it is possible. The scheduling algorithm used by our controller schedules a new request every 9 Rambus cycles (36 ns), which corresponds to a peak data throughput of 222 MBytes/s. Our controller handles individual word accessess, thus it could be used in a system that requires high data rates with increased bandwidth requirements, and accesses to non-sequential memory words, for example a supercomputer accessing non-cached vector elements with random stride. The chip was designed using the ES2 1.0 micron CMOS standard cell proccess and it was successfully simulated for speeds up to 18.8 MHz (53 ns).
KEYWORDS: memory controller, Rambus controller, RDRAM controller, synchronous DRAM, memory interleaving.
Note (Jan. 1999): Back in 1993, when this work was performed, the Rambus protocol was not designed for interleaving. Nowadays, the Rambus protocol II, runs at higher speed and provides for interleaved accesses in a natural way.
© Copyright 1994 by FORTH.
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