Pipelined Memory Shared Buffer for VLSI Switches

M. Katevenis: ``A High-Throughput Data Buffer'', Foundation for Research & Technology -- Hellas (FORTH), Heraklion Crete Greece; USA Patent Number 5,774,653 (30 June 1998); European Patent Application No. 95410074.9 (27 July 1995); Greek Patent Application No. 940100383 (2 Aug. 1994).

Pipelined Memory shared buffers are used in the Telegraphos project switches, and in the ATLAS I single-chip ATM gigabit switch.

We present a new organization for a shared buffer with its associated switching and cut-through functions. It is simpler and smaller than wide or interleaved organizations, and it is particularly suitable for VLSI technologies. It is based on multiple memory banks, addressed in a pipelined fashion. The first word of a packet is transferred to/from the first bank, followed by a ``wave'' of similar operations for the remaining words in the remaining banks. An FPGA-based prototype is operational, while standard-cell and full-custom chips are being submitted for fabrication. Simulation of the full-custom version indicates that, even in a conservative 1-micron CMOS technology, a 64 Kbit central buffer for an 8x8 switch operates at 1 Gbps/link (worst case) and fits in 45 mm² including crossbar and cut-through.

KEYWORDS: crossbar switch, shared buffering, input queueing, multi-port buffer, pipelined memory, gigabit VLSI switch buffer.

Animated Illustration of the Pipelined Memory opeartion: click here

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© Copyright 1995 by ACM; 0-89791-711-1/95/0008...$3.50
Published in the Proceedings of the ACM SIGCOMM '95 Conference, Cambridge, MA USA, 30 Aug. - 1 Sep. 1995, pp. 39-48.
Permission to make digital/hard copies of all or part of this material without fee is granted provided that the copies are not made or distributed for profit or commercial advantage, the ACM copyright/server notice, the title of the publication and its date appear, and notice is given that copying is by permission of the Association of Computing Machinery, Inc. (ACM). To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee.

In this work we designed a pipelined memory with a throughput of 25 Gbits/s (16 Gbits/s in the worst case), enough for 8 incoming and 8 outgoing links at gigabit per second rates. Full-custom design techniques were employed to achieve small area and high speed. The full-custom implementation of the pipelined memory pays off the long development time, as our implementation is 4 times smaller and 3 times faster than the pipelined memory of a semicustom switch chip that was recently designed by our research group. Besides the pipelined memory that was implemented, three other floorplan organizations were investigated which can be used for pipelined memories of different specifications.

A test chip containing the pipelined memory and semi-custom control and interface circuits was fabricated. This chip, although it revealed some minor design errors, operates correctly for clock frequencies of up to 80MHz, consuming 2.75 Watts.

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© Copyright 1995 by FORTH.
Permission to make digital/hard copies of all or part of this material without fee is granted provided that the copies are made for personal use, they are not made or distributed for profit or commercial advantage, the FORTH copyright notice, the title of the publication and its date appear, and notice is given that copying is by permission of the Foundation for Research & Technology -- Hellas (FORTH). To copy otherwise, to republish, to post on servers, or to redistribute to lists, requires prior specific written permission and/or a fee.