Design and Implementation of a 1.2 Gbit/s ATM Cell Buffer using a Synchronous DRAM Chip

by George N. Glykopoulos

Technical Report FORTH-ICS/TR-221
July 1998

Computer Architecture and VLSI Systems Division,
Institute of Computer Science (ICS), FORTH
Science and Technology Park of Crete, P.O.Box 1385, Heraklion, Crete, GR 711 10 Greece

Master of Science Thesis, Department of Computer Science, University of Crete

ABSTRACT:

High speed networks require high throughput memories to store cells or packets. Synchronous Dynamic RAM (SDRAM) chips provide both high storage capacity and high throughput, and are thus an appropriate technology for building such cell or packet buffers. One 16Mbit SDRAM chip with a 16-bit data interface provides 40K cell storage and 1.2Gbit/s throughput when used as an ATM cell buffer.

The purpose of this work was to demonstrate this capability in a working prototype, gaining familiarity with the practical details of SDRAM and SONET operation, and PCB implementation with 100MHz clocks. The prototype that was designed, manufactured and successfully tested, is an 8-layer PCB with two SONET OC-3 links (2 x 155.52Mbit/s incoming and 2 x 155.52Mbit/s outgoing throughput), interfaced to an SDRAM chip using two ALTERA FPGA's. The board also includes a microprocessor interface and PLL-driven clock generators/drivers.

The Full Technical Report is Available in:

© Copyright 1998 by FORTH.
Permission to make digital/hard copies of all or part of this material without fee is granted provided that the copies are made for personal use, they are not made or distributed for profit or commercial advantage, the FORTH copyright notice, the title of the publication and its date appear, and notice is given that copying is by permission of the Foundation for Research & Technology -- Hellas (FORTH). To copy otherwise, to republish, to post on servers, or to redistribute to lists, requires prior specific written permission and/or a fee.


[ Original Site in Greece ] [ North European Mirror ] [ North American Mirror ]
[ Up to Packet Switch Architecture R&D at CARV-ICS-FORTH ]
© copyright ICS-FORTH, Crete, Greece.
Last updated: January 1999, by M. Katevenis.